Digital electronic circuits may utilize high frequency clock signals, within the range of multiple GHz. Those signals are typically distributed over a wide area of the chip (>400 mm2), thereby travelling a large distance (many millimeters), while the arrival times of the signals have to be within small time windows (less than 10 ps). To distribute the signals, a clock tree is used and the distribution area is divided into smaller pieces, every piece having disjoint parts of the clock tree. The arrival times of the clock signal will be impacted by process, voltage and temperature variations on the disjoint parts of the clock distribution network for any adjacent sub-mesh pair.